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copyright ? alliance semiconductor. all rights reserved. as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 1 of 25 5v 256k x 16 cmos dram (fast page mode) ? pin designation pin(s) description a0 to a8 address inputs ras row address strobe i/o0 to i/o15 input/output oe output enable ucas column address strobe, upper byte lcas column address strobe, lower byte we read/write control v cc power (+5v 10%) gnd ground features ? organization: 262,144 words 16 bits high speed - 25/30/35/50 ns ras access time - 12/16/18/25 ns column address access time - 7/10/10/10 ns cas access time low power consumption - active: 770 mw max (asas4c256k16fo-50) - standby: 5.5 mw max, cmos i/o fast page mode as4c256k16fo-50 timings are also valid for as4c256k16fo-60. refresh - 512 refresh cycles, 8 ms refresh interval -ras -only or cas -before-ras refresh or self-refresh - self-refresh option is available for new generation device only. contact alliance for more information. read-modify-write ttl-compatible, three-state i/o jedec standard packages - 400 mil, 40-pin soj - 400 mil, 40/44-pin tsop ii single 5v power supply/built-in v bb generator latch-up current > 200 ma pin arrangement 40 39 38 37 36 35 34 33 32 31 gnd i/o15 i/o14 i/o13 i/o12 gnd i/o11 i/o10 i/o9 i/o8 soj 30 29 28 27 26 25 24 23 22 21 nc lcas ucas oe a8 a7 a6 a5 a4 gnd 1 2 3 4 5 6 7 8 9 10 v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 11 12 13 14 15 16 17 18 19 20 nc nc we ras nc a0 a1 a2 a3 v cc v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 nc nc we ras nc a0 a1 a2 a3 v cc v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 i/o8 nc lcas ucas oe a8 a7 a6 a5 a4 v ss 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 tsop ii asc256k16fo asc256k16fo selection guide symbol ?25 ?30 ?35 ?50 unit maximum ras access time t rac 25 30 35 50 ns maximum column address access time t caa 12 16 18 25 ns maximum cas access time t cac 7101010ns maximum output enable (oe ) access time t oea 7101010ns minimum read or write cycle time t rc 40 65 70 85 ns minimum edo page mode cycle time t pc 12 12 14 25 ns maximum operating current i cc1 200 180 160 140 ma maximum cmos standby current i cc2 2.0 2.0 2.0 2.0 ma
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 2 of 25 functional description the as4c256k16fo is a high-performance 4 megabit cmos dynamic random access memory (dram) device organized as 262,144 words 16 bits. the as4c256k16fo is fabricated with advanced cmos technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. the as4c256k16fo features a high-speed page mode operation in which high speed read, write and read-write are performed on any of the 512 16 bits defined by the column address. the asynchronous column address uses an extremely short row address capture time to ease the system-level timing constraints associated with multiplexed addressing. output is tri-stated b y a column address strobe (cas ) which acts as an output enable independent of ras . very fast cas to output access time eases system design. refresh on the 512 address combinations of a0?a8 during an 8 ms period is accomplished by performing any of the following: ras -only refresh cycles hidden refresh cycles cas -before-ras refresh cycles normal read or write cycles self-refresh cycles. * the as4c256k16fo is available in standard 40-pin plastic soj and 44-pin tsop ii packages compatible with widely available automated testing and insertion equipment. system level features include single power supply of 5v 10% tolerance and direct interface with ttl logic families. logic block diagram recommended operating conditions * self-refresh option is available for new generation device only. contact alliance for more information. parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v gnd 0.0 0.0 0.0 v input voltage v ih 2.4 ? v cc + 1 v v il ?1.0 ? 0.8 v 512 512 16 array (4,194,304) sense amp a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd addreess buffers a8 row decoder column decoder oe ras ucas we lcas i/o0 to i/o15 substrate bias generator data i/o buffer refresh controller ras clock generator cas clock generator we clock generator
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 3 of 25 absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics (v cc = 5 10%, gnd = 0v, t a = 0 c to +70 c) parameter symbol min max unit input voltage v in ?1.0 +7.0 v output voltage v out ?1.0 +7.0 v power supply voltage v cc ?1.0 +7.0 v operating temperature t opr 0+70c storage temperature (plastic) t stg ?55 +150 c soldering temperature time t solder ?260 10 c sec power dissipation p d ?1w short circuit output current i out ?50ma latch-up current 200 ? ma parameter symbol test conditions ?25?30?35?50 unit note min max min max min max min max input leakage current i il 0v v in + 5.5v pins not under test = 0v ?1010?1010?1010?1010 a output leakage current i ol d out disabled, 0v v out + 5.5v ?1010?1010?1010?1010 a operating power supply current i cc1 ras , ucas , lcas , address cycling; t rc = min ?200?180?160?140ma1,2 ttl standby power supply current i cc2 ras = ucas = lcas = vih ? 2.0 ? 2.0 ? 2.0 ? 2.0 ma average power supply current, ras refresh mode i cc3 ras cycling, ucas = lcas = v ih , t rc = min ?120?200?190?140ma1 fast page mode average power supply current i cc4 ras = ucas = lcas = v il , address cycling: t sc = min ?130?190?180? 70ma1,2 cmos standby power supply current i cc5 ras = ucas = lcas = v cc ? 0.2v ? 0.60 ? 1.0 ? 1.0 ? 1.0 ma cas -before-ras refresh power supply current i cc6 ras , ucas , lcas , cycling; t rc = min ?120?200?190?140ma1 output voltage v oh i out = ? 5.0 ma 2.4 ? 2.4 ? 2.4 ? 2.4 ? v v ol i out = 4.2 ma ? 0.4 ? 0.4 ? 0.4 ? 0.4 v self refresh current i cc7 ras = ucas = lcas = v il , we = oe = a0 ? a8 = v cc ?0.2v, dq0 ? dq15 = v cc ? 0.2v, 0.2v are open ? 2.0 ? 2.0 ? 2.0 ? 2.0 ma
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 4 of 25 ac parameters common to all waveforms (v cc = 5v 10%, gnd = 0v, t a = 0 c to +70 c) read cycle (v cc = 5v10%, gnd = 0v, t a = 0 c to + 70 c) standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t rc random read or write cycle time 45 ? 65 ? 70 ? 85 ? ns t rp ras precharge time 15 ? 25 ? 25 ? 25 ? ns t ras ras pulse width 25 75k 30 75k 35 75k 50 75k ns t cas cas pulse width 4 ? 5 ? 6 ? 10 ? ns t rcd ras to cas delay time 10 17 15 20 16 24 15 35 ns 6 t rad ras to column address delay time8 13101411171525 ns 7 t rsh(r) cas to ras hold time (read cycle) 7 ? 10 ? 10 ? 10 ? ns t csh ras to cas hold time 20 ? 30 ? 35 ? 50 ? ns t crp cas to ras precharge time 5?5?5?5?ns t asr row address setup time 0?0?0?0?ns t rah row address hold time 5?5?6?9?ns t t transition time (rise and fall) 1.5 50 1.5 50 1.5 50 3 50 ns 4,5 t ref refresh period ?8?8?8?8ms3 t clz cas to output in low z 0?0?0?3?ns8 standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t rac access time from ras ? 25 ? 30 ? 35 ? 50 ns 6 t cac access time from cas ?7 ?10 ? 10 ?10ns6,13 t aa access time from address ? 12 ? 16 ? 18 ? 25 ns 7,13 t ar(r) column add hold from ras 19 ? 26 ? 28 ? 30 ? ns t rcs read command setup time 0 ? 0 ? 0 ? 0 ? ns t rch read command hold time to cas 0?0?0 ?0?ns9 t rrh read command hold time to ras 0?0?0 ?0?ns9 t ral column address to ras lead time 12 ? 16 ? 18 ? 25 ? ns t cpn cas precharge time 4?3?4 ?5?ns t off output buffer turn-off time 0 6 0 8 0 8 0 8 ns 8,10
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 5 of 25 write cycle (v cc = 5v 10%, gnd = 0v, t a = 0 c to +70 c) read-modify-write cycle (v cc = 5v 10%, gnd = 0v, t a = 0 c to +70 c) fast page mode cycle (v cc = 5v 10%, gnd = 0v, t a = 0 c to +70 c) standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t asc column address setup time 0?0?0?0? ns t cah column address hold time 5?5?5?9? ns t aw r column address hold time to ras 19 ? 26 ? 28 ? 30 ? ns t wcs write command setup time 0?0?0?0? ns 11 t wch write command hold time 5?5?5?9? ns 11 t wcr write command hold time to ras 19 ? 26 ? 28 ? 30 ? ns t wp write command pulse width 5 ? 5 ? 5 ? 9 ? ns t rw l write command to ras lead time 7 ? 10 ? 11 ? 12 ? ns t cwl write command to cas lead time 5 ? 10 ? 11 ? 12 ? ns t ds data-in setup time 0?0?0?0? ns 12 t dh data-in hold time 5?5?5?9? ns 12 t dhr data-in hold time to ras 19 ? 26 ? 28 ? 30 ? ns standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t rw c read-write cycle time 100 ? 100 ? 105 ? 120 ? ns t rw d ras to we delay time 34 ? 50 ? 54 ? 60 ? ns 11 t cwd cas to we delay time 17 ? 26 ? 28 ? 30 ? ns 11 t aw d column address to we delay time 21 ? 32 ? 35 ? 40 ? ns 11 t rsh(w) cas to ras hold time (write) 7 ? 10 ? 10 ? 12 ? ns t cas(w) cas pulse width (write) 15 ? 15 ? 15 ? 15 ? ns standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t pc read or write cycle time 8 ? 12 ? 14 ? 25 ? ns 14 t cap access time from cas precharge ? 14 ? 19 ? 21 ? 23 ns 13 t cp cas precharge time 3?3?4?5? ns t pcm fast page mode rmw cycle 56 ? 56 ? 58 ? 60 ? ns t crw page mode cas pulse width (rmw) 44 ? 44 ? 46 ? 50 ? ns t rasp ras pulse width 25 75k 30 75k 35 75k 50 75k ns
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 6 of 25 refresh cycle (v cc = 5v 10%, gnd = 0v, t a = 0 c to +70 c) output enable (v cc = 5v 10%, gnd = 0v, t a = 0 c to +70 c ) self refresh cycle (v cc = 5v 10%, gnd = 0v, t a = 0 c to +70 c ) notes 1i cc1 , i cc3 , i cc4 , and i cc6 depend on cycle rate. 2i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 3 an initial pause of 200 s is required after power-up followed by any 8 ras cycles before proper device operation is achieved. in the case of an internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). 4 ac characteristics assume t t = 5 ns. all ac parameters are measured with a load equivalent to two ttl loads and 100 pf, v il (min) gnd and v ih (max) v cc . 5v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 6 operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the speci- fied t rcd (max) limit, then access time is controlled exclusively by t cac . 7 operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the speci- fied t rad (max) limit, then access time is controlled exclusively by t aa . 8 assumes three state test load (5 pf and a 380 ? thevenin equivalent). 9either t rch or t rrh must be satisfied for a read cycle. 10 t off (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11 t wcs , t wch , t rw d , t cwd and t awd are not restrictive operating parameters. they are included in the datasheet as electrical characteristics only. if t ws t ws (min) and t wh t wh (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. if t rw d t rw d (min), t cwd t cwd (min) and t aw d t aw d (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12 these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read-write cycles. 13 access time is determined by the longest of t caa or t cac or t cap . 14 t asc t cp to achieve t pc (min) and t cap (max) values. 15 these parameters are sampled, but not 100% tested. standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t csr cas setup time (cas -before-ras )10?10?10?10? ns 3 t chr cas hold time (cas -before-ras )7?7?8?10?ns3 t rpc ras precharge to cas hold time 0 ? 0 ? 0 ? 0 ? ns t cpt cas precharge time (cas -before-ras counter test) 8?8?8?8?ns standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t roh ras hold time referenced to oe 5?5?5?5?ns t oea oe access time ? 8 ? 10 ? 10 ? 10 ns t oed oe to data delay 5 ? 5 ? 5 ? 8 ? ns t oez output buffer turnoff delay from oe ? 6?8?8?8 ns 8 t oeh oe command hold time 5 ? 8 ? 8 ? 8 ? ns standard symbol parameter ?25 ?30 ?35 ?50 unit notes min max min max min max min max t rass ras pulse width (cbr self refresh) 100k ? 100k ? 100k ? 100k ? ns t rps ras precharge time (cbr self refresh) 85 ? 85 ? 85 ? 85 ? ns t chs cas hold time (cbr self refresh) 30 ? 30 ? 30 ? 30 ? ns
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 7 of 25 key to switching waveforms read cycle waveform undefined/don?t care falling input rising input t ras t rc t rp t rsh t rad t rch t roh t cac t oea t off t oez ras ucas , lcas address we oe i/o col address row address t crp t csh t rcd t asc t cah t cas t ar t ral t rah t rcs t aa t clz t rrh data out t asr t rac
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 8 of 25 upper byte read waveform lower byte read waveform t ras t rc t rp t crp t rcd t rsh t csh t crp t crp t asr t rah t rad t ral t cah t rcs t rrh t rch t clz t cac t oez t off row column data out ras ucas lcas address we oe upper i/o lower i/o t roh t asc t rac t oea t aa t cas t roh t oea t ras t rc t rp t crp t rcd t rsh t crp t crp t asr t rah t rad t ral t cah t rrh t rch t clz t cac t rac t oez t off row column data out ras lcas ucas address we oe upper i/o lower i/o t csh t asc t rcs t aa t cas
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 9 of 25 early write waveform t ras t rc t rp t crp t rsh t rcd t csh t cas t rah t rad t asc t aw r t cah t wcs t cwl t rw l t wch t wp t ds t dh t dhr col address data in ras ucas , lcas address we oe i/o row address t wcr t ral t asr
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 10 of 25 upper byte early write waveform t ras t rc t rp t rah t rad t aw r t crp t asc t cah t rsh t rcd t csh t crp t crp t rpc t rw l t wcs t wp t ds t dh t dhr row address column address data in ras address ucas lcas we oe upper i/o lower i/o t asr t ral t cas t cwl t wch t wcr
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 11 of 25 lower byte early write waveform write waveform t rc t ras t rp t rad t aw r t crp t rpc t crp t asc t cah t rsh t rcd t csh t crp t rw l t wp t wcs t wcr t wch t ds t dh t dhr row address column address data in ras address ucas lcas we oe upper i/o lower i/o t cwl t rah t cas t ral t asr row address t ras t rc t rp t crp t rsh t rcd t csh t cas t rah t ral t rad t cah t cwl t rw l t wcr t oeh t oed t ds t dh data in ras ucas , address we oe i/o col address t wp t asc t aw r t asr lcas t dhr
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 12 of 25 upper byte write waveform t ras t rc t rp t ral t rad t asc t cah t csh t crp t crp t rpc t rw l t wp t oeh t ds t dh t oed row address column address data in ras address ucas lcas we oe upper i/o lower i/o t crp t aw r t rah t rcd t cas t rsh t cwl t asr
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 13 of 25 lower byte write waveform read-modify-write waveform t rc t ras t rp t rah t rad t acs t cah t rsh t csh t crp t crp t rpc t rw l t wp t oeh t ds t dh row address column address data in ras address lcas ucas we oe upper i/o lower i/o t crp t rcd t cas t cwl t aw r t ral t asr t ras t rw c t rp t crp t rsh t rcd t csh t cas t rad t ral t ar t cah t cwl t cwd t rw l t aw d t wp t oea t clz t cac t aa t ds t dh row address col address data in data out ras ucas , address we oe i/o t rah t rw d t rcs t rac t oez t oed t asc t asr lcas
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 14 of 25 upper byte read-modify-write waveform t rw c t ras t rp t crp t rsh t rcd t csh t cas t crp t crp t rpc t ral t cah t rw l t aw d t wp t cwd t oea t ds t clz t aa t rac t cac t oez t oed row column address data in data out data out ras ucas lcas address we oe upper input upper output lower input lower output t acs t rw d t cwl t oed t rcs t rah t asr t rad
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 15 of 25 lower byte read-modify write waveform t rw c t ras t rp t crp t rpc t crp t rsh t rcd t csh t cas t crp t ral t rad t acs t cah t rcs t rw l t wp t oea t oed t ds t clz t oez row column address data in data out ras ucas lcas address we oe upper input upper output lower input lower output t rah t aw d t cwl t cwd t cac t rw d t asr t aa t rac data out
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 16 of 25 fast page mode read waveform fast page mode byte read waveform t asc row t rasp t rp t crp t rcd t cas t csh t rsh t pc t asr t rad t rch t rcs t rrh t rch t oea t oea t aa t rac t cac t oez t cap data out data out data out col address col address col address ras ucas , address we oe i/o t ar t rah t cah t ral t rcs t clz t cp t off lcas t rasp t rp t cas t csh t rsh t cas t cas t crp t crp t cas t cp t rpc t rah t rad t asc t cah t asc t rcs t oea t oez t off t cac t rac t off t oez t clz t aa t cac t cap t off t oez row column 1 column 2 column n data out 1 data out n data out 2 ras ucas lcas address we oe upper i/o lower i/o t clz t cap t aa t clz t cac t oea t rcs t rch t oea t cah t ral t pc t pc t cah t asc t rcd t rch t rcs t asr t crp t aa t cp
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 17 of 25 fast page mode early write waveform fast page mode byte early write waveform t rah t rasp t rw l t asc t wcs t ral t wch t cwl t wp t ds t dh t oed t cas row address col address col address col address data in data in data in ras ucas , address we oe i/o t pc t cah t csh t rcd t oeh t hdr t ar t rad t asr t crp lcas t rsh t cp t rasp t rp t cas t csh t rsh t cas t crp t crp t cp t cp t rpc t rad t asc t ral t wcs t cwl t wcs t wch t wcs t cwl t rw l t ds t dh t ds t dh t ds t dh row column 1 column 2 column n data in 1 data in n data in 2 ras ucas lcas address we oe upper i/o lower i/o t pc t rah t asc t wch t wp t wp t cwl t wp t wch t cah t rcd t pc t cas t cah t cah t asc t crp t asr
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 18 of 25 fast page mode read-modify-write waveform cas -before-ras refresh waveform (we = v ih ) ras -only refresh waveform (we = oe = v ih or v il ) t cac t ds t clz t cac t rac t rasp t rp t rcd t csh tcas t cp t crp t asr t cah t cah t ral t cah t cwd t aw d t cwd t cwl t cwd t awd t rw l t wp t oez t oea t ds t clz t cac t cap row ad col ad col address col ad data out data in data in data out data out data in ras ucas , address we oe i/o t rad t rah t rw d t rcs t cwl t oea t aa t dh t clz t oed t pcm lcas t rp t rc t ras t rpc t cpn t csr t chr t off ras ucas , i/o lcas t ras t rp t rc t crp t rpc t ars t rah row address ras ucas , address lcas
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 19 of 25 fast page mode byte read-modify-write waveform data out 1 t rasp t rp t rcd t cas t csh t crp t cp t cp t cah t asc t cah t asc t ral t cwd t cwl t cwl t cwd t wp t rw l t oea t dh t oez t dh t clz t cac t aa t cap t oez data in n data out n data out 2 data in 2 rc 1 c 2 c n ras ucas lcas address we oe upper input upper output lower input lower output t pcm t cas t rsh t cas t aw d t cah t aw d t asc t wp t cwl t wp t oea t oea t oed t ds t cap t ds t oed t dh t oez t clz t oed t ds t aa t cac t clz t cwd t awd t crp t rad t rah t asr t rcs t rw d t rac data in 1 t aa t cac
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 20 of 25 hidden refresh waveform (read) hidden refresh waveform (write) t aa t chr t ras t rc t pr t ras t rc t pr t crp t rcd t rsh t crp t asr t rad t asc t rrh t oea t clz t cac t oez t off col address row data out ras cas address we oe i/o t ar t rah t rcs t rac t ras t rc t rp t crp t rcd t rsh t asr t rah t rad t ar t cah t wcs t wch t ds t dh data in col address row address ras ucas , address we i/o oe t asc t rw l t wcr t wp t dhr t ral lcas
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 21 of 25 cas before ras refresh counter test waveform t ras t rsh t rp t csr t chr t cpt t cas t cah t clz t cac t rch t rrh t roh t oea t rw l t cwl t wcs t wp t wch t ds t dh t rcs t oea t ds t dh col address data out data in data out data in ras ucas , lcas address i/o we oe we i/o oe we oe i/o t oed t aa t clz t cac t oez t wp t cwl t rcs t aa t off t aw d t cwd t ral read cycle write cycle read-write cycle
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 22 of 25 cas -before-ras self refresh cycle typical ac and dc characteristics t rp t rass t rpc t cp t chs t cez ras ucas , dq lcas t rps t csr t rpc supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t rac ambient temperature (c) ?55 80 125 35 ?10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t rac load capacitance (pf) 50 200 250 150 100 30 40 60 70 50 80 90 100 typical access time typical access time t rac vs. ambient temperature t a vs. load capacitance c l vs. supply voltage v cc t a = 25c ?70 ?60 ?50 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.0 10 30 40 20 50 60 70 supply current (ma) typical supply current i cc ambient temperature (c) ?55 80 125 35 ?10 0.0 10 30 40 20 50 60 70 supply current (ma) typical supply current i cc cycle rate (mhz) 28 10 6 4 0.0 5 15 20 10 25 30 35 power-on current (ma) typical power-on current i po vs. ambient temperature t a vs. cycle rate 1/t rc vs. supply voltage v cc
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 23 of 25 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0 5 15 20 10 25 30 35 refresh current (ma) typical refresh current i cc3 ambient temperature (c) 0.0 60 80 40 20 refresh current (ma) typical refresh current i cc3 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 stand-by current (ma) typical ttl stand-by current i cc2 vs. ambient temperature t a vs. supply voltage v cc vs. supply voltage v cc 0 5 15 20 10 25 30 35 ambient temperature (c) 060 80 40 20 0.0 0.5 1.5 2.0 1.0 2.5 3.0 3.5 stand-by current (ma) typical ttl stand-by current i cc2 output voltage (v) 0.0 1.5 2.0 1.0 0.5 0.0 10 30 40 20 50 60 70 output sink current (ma) typical output sink current i ol output voltage (v) 0.0 3.0 4.0 2.0 1.0 0.0 10 30 40 20 50 60 70 output source current (ma) typical output source current i oh vs. output voltage v ol vs. output voltage v oh vs. ambient temperature t a fast page mode current (ma) ambient temperature (c) 060 80 40 20 0.0 5 15 20 10 25 30 35 fast page mode current (ma) typical fast page mode current i cc4 supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.0 5 15 20 10 25 30 35 typical fast page mode current i cc4 vs. supply voltage v cc vs. ambient temperature t a
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 24 of 25 package dimensions capacitance (f = 1 mhz, t a = room temperature, v cc = 5v 10%) parameter symbol signals test conditions max unit input capacitance c in1 a0 to a8 v in = 0v 5 pf c in2 ras , ucas , lcas , we , oe v in = 0v 7 pf i/o capacitance c i/o i/o0 to i/o15 v in = v out = 0v 7 pf 44-pin tsop ii min (mm) max (mm) a1.2 a 1 0.05 a 2 0.95 1.05 b0.300.45 c 0.127 (typical) d 18.28 18.54 e 10.03 10.29 h e 11.56 11.96 e 0.80 (typical) l0.400.60 d h e 1234567891011121314 4443424140393837363534333231 1516 3029 17181920 28272625 c l a 1 a 2 e 40/44-pin tsop ii 0?5 21 24 22 23 e a b 40-pin soj 400 mil min max a 0.128 0.148 a 1 0.026 - a 2 1.105 1.115 b 0.026 0.032 b0.020 c 0.007 0.013 d 1.020 1.035 e0.370 (typical) e 1 0.395 0.405 e 2 0.435 0.445 e 0.050 (typical) e d e 1 pin 1 b b a 1 a 2 c e 2 seating plane e 2 a 40-pin soj
? as4c256k16fo 4/11/01; v.0.9.1 alliance semiconductor p. 25 of 25 ordering codes part numbering system ?25 ns ?30 ns ?35 ns ?50 ns as4c256k16f0-25jc as4c256k16f0-30jc as4c256k16f0-35jc as4c256k16fo-50jc as4c256k16f0-25ji as4c256k16f0-30ji as4c256k16f0-35ji as4c256k16fo-50ji as4c256k16f0-25tc AS4C256K16F0-30TC as4c256k16f0-35tc as4c256k16fo-50tc as4c256k16f0-25ti as4c256k16f0-30ti as4c256k16f0-35ti as4c256k16fo-50ti as4c 256k16f0 ?xx x c/i dram prefix device number ras access time package: j = plastic soj, 400 mil, 40-pin t = tsop ii, 400 mil, 40/44-pin temperature range: c= commercial (0 c to 70 c) i= industrial (-40c to 85c)

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